THE SIGNAL IN ONE SENTENCE
India is shipping semiconductor work into the world before its flagship wafer fabrication plant has produced a wafer. Electronics and IT Minister Ashwini Vaishnaw told Financial Express at SEMICON India 2026 that Indian assembly, testing, marking and packaging facilities are already exporting to Japan, that chips made or designed in India are entering products exported to Germany and Switzerland, and that one chip displayed at the conference is exported to China. Those are meaningful steps, but the nouns matter. Designing a chip is not fabricating its silicon. Packaging and testing a die is not growing the front-end manufacturing capability that turns a blank wafer into working circuits. A chip inside an exported device is not necessarily a direct chip export. Vaishnaw also said the Tata Electronics and PSMC fab under construction at Dholera is expected to produce its first wafer in 2028. SEMI says three of 12 approved projects have entered commercial production, while its own value-chain map separates design, wafer fabrication, assembly, test, packaging, materials, equipment, and systems. The plain signal is that a semiconductor ecosystem can become useful before it becomes complete. India should claim the steps it can document, name the product and value added at each step, and leave the empty wafer pedestal empty until a measured wafer actually comes off the line.
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WHAT ACTUALLY CHANGED
Financial Express reported on September 18 from a fireside interview with Vaishnaw at SEMICON India 2026. He said assembly, testing, marking and packaging units in India were exporting to Japan, chips were entering products exported to Germany and Switzerland, and one chip shown at the event was exported to China. The report does not name the chips, facilities, customers, shipment volumes, export values, customs records, process nodes, or Indian share of value added.
The minister described a future in which more chips are both designed and made end to end in India. That future tense matters. The evidence he offered spans several current activities: domestic design, commercial packaging and test, equipment localization, and components inside exported electronics. It does not establish that the same product was designed, fabricated, packaged, tested, and directly exported from India.
Vaishnaw said Tata Electronics and Taiwanese partner PSMC expect the Dholera facility in Gujarat to produce its first wafer in 2028. A first-wafer target is an engineering milestone, not commercial volume. After an initial wafer, a fab still has to demonstrate repeatable yield, qualification, customer acceptance, delivery, and economically useful production.
SEMI said before the conference that three of 12 semiconductor projects approved under the first government program had commenced commercial production. Its announcement does not identify all three in that sentence or publish their product mix, capacity, utilization, yield, customers, or export results. Commercial production can include assembly and packaging projects without implying that India already operates the Dholera front-end fab.
The official conference map is unusually helpful because it refuses to compress the industry into one magic factory. SEMICON India separates semiconductor design and intellectual property, wafer fabrication, assembly and test, infrastructure, machines, materials, chemicals, packaging, compound semiconductors, electronics components, systems manufacturing, AI, and high-performance computing.
Reuters reported on September 17 that Nexperia agreed to work with Tata Electronics on power-control chips at Dholera and on assembly and testing at Tata's Jagiroad packaging plant. The Dholera work depends on a fab that is still being built. The partnership is evidence of intended customers and ecosystem formation, not evidence that Dholera wafers are already shipping.
The event itself ran from September 17 to 19 in New Delhi and was jointly organized by the India Semiconductor Mission and SEMI. SEMI described more than 500 exhibitors and a program stretching from silicon to complete systems. Conference scale measures participation. It does not measure domestic manufacturing depth, so the article keeps announcements, operating facilities, and future capacity in separate columns.
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WHY THIS MATTERS
AI infrastructure depends on far more than the newest accelerator. Power-management chips, networking parts, memory interfaces, sensors, controllers, packaging, substrates, test equipment, servers, cooling systems, and reliable electronics manufacturing all shape whether a country can build and operate useful compute. India can gain real capability in those layers before it fabricates a leading-edge processor.
Packaging is not the consolation prize at the semiconductor Olympics. Advanced packaging connects dies, memory, power, and high-speed links into working systems. Testing catches failures before those systems reach cars, factories, hospitals, phones, and data centers. The mistake is not celebrating packaging. The mistake is calling every package a domestically fabricated chip.
Design creates intellectual property and skilled work, but design sovereignty depends on the rest of the chain. A domestic team may tape out a valuable chip while relying on a foreign foundry, foreign electronic-design software, imported equipment, imported wafers, and overseas packaging. The right scorecard shows which dependency changed instead of awarding one flag to the whole object.
The first wafer will be exciting and incomplete. Early production can have low yield, long qualification cycles, limited process options, and customers that keep backup suppliers. A useful fab must repeatedly turn inputs into conforming dies at a cost, quality, security level, and schedule customers can accept. One ceremonial wafer cannot carry that argument by itself.
Export claims need a traceable denominator. A chip shipped directly to a Japanese customer, a packaged die returned to its owner, and an Indian-designed component inside a phone exported to Germany all create different revenue, learning, and leverage. Publishing units, value, destination, customer type, and domestic transformation would let India show progress without making readers reverse-engineer the sentence.
Industrial policy should reward verified learning, not only construction. Equipment installation, qualified suppliers, trained operators, safe chemical handling, water and power reliability, defect reduction, customer qualification, and local repair capacity determine whether a subsidized plant becomes a durable capability. These slower measures are less photogenic and more important than another groundbreaking shovel.
Other countries should pay attention because India is trying to enter the chain through several doors at once. If design, packaging, equipment components, electronics systems, and a future fab reinforce one another, the country could diversify a concentrated global supply chain. If the parts remain isolated, public money may produce impressive sites with weak utilization and limited local value capture.
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WHERE IT COULD HELP
- Publish a product-level semiconductor ledger naming the designer, fabrication country, process node, packaging and test site, product category, customer qualification status, shipment volume, export value, destination, and estimated domestic value added without exposing protected customer secrets
- Report every project by the same milestones: construction complete, equipment installed, pilot line operating, first wafer or package, engineering samples, qualified product, commercial shipment, utilization, yield range, repeat customer, and audited public support paid
- Label export statistics by transaction type, separating direct chip exports, packaging and test services, dies returned to foreign owners, domestically designed chips fabricated abroad, and chips embedded in exported electronics
- Tie future incentives to independent evidence of workforce retention, supplier qualification, repair capability, safety performance, water and power readiness, defect reduction, customer diversification, domestic research, and value added rather than plant area alone
- Build shared test, reliability, design-tool, prototyping, and failure-analysis facilities that startups and universities can access without owning a fab, then publish usage, queue times, successful tape-outs, and products reaching customers
- For AI programs, map the complete hardware bill from accelerator and memory to power, network, packaging, board, server, cooling, and software, then identify which Indian capability is operating, qualified, under construction, announced, or still imported
KEEP A HAND ON THE WHEEL
The export statements come from India's electronics and IT minister in a direct Financial Express interview. They are government claims, not a product-by-product export audit. The report distinguishes ATMP exports to Japan, chips inside products exported to Germany and Switzerland, and one displayed chip exported to China, but it does not publish the product names, facilities, companies, buyers, shipment counts, values, customs classifications, process nodes, yield, or domestic value added. SEMI says three of 12 approved projects have started commercial production, but its announcement does not provide a comparable operating table. The Dholera first-wafer date is a 2028 target. A partnership, memorandum, construction milestone, installed tool, first wafer, qualified product, commercial shipment, and profitable high-yield volume are separate events. Watch for named shipments, official trade classifications, the three operating projects, verified customer qualifications, Tata's construction and equipment milestones, Jagiroad production evidence, Dholera's first wafer, yield and utilization disclosures, and a public account of subsidies paid against milestones achieved.
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TERMS WORTH KEEPING
OPEN GLOSSARY CARD
Wafer fabrication
The front-end manufacturing process that builds many integrated circuits together on a semiconductor wafer through repeated deposition, patterning, etching, doping, cleaning, and inspection steps.
OPEN GLOSSARY CARD
ATMP
Assembly, testing, marking, and packaging, the set of back-end steps that turns fabricated dies into identified, protected, connected, and verified chip products.
OPEN GLOSSARY CARD
Tape-out
The point when a completed chip design is released for mask preparation and fabrication after its digital files pass the required design checks.
SOURCES AND VERIFICATION STATUS
This article was written from the materials below. Product claims and dates were checked against those sources on September 18, 2026.
PUBLICATION RECEIPT: Revision 1. Published September 18, 2026.
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